Design of Low Power and Area Efficient Cmos Full Adder Using Pass Transistor Logic

ABSTRACT

The scaling based advantages of a VLSI or ULSI circuits has been reaped over the years showing effective solutions for the portable appliances. Irrespective of the technology VLSI circuits can be made more efficient with the exploitation of architectural advantages. One of the primitive architectural schemes is based on use of pass transistor logic. In this paper, the design of a low power and area efficient hybrid full adder is presented using both CMOS logic and also pass transistor logic. The design involves minimal number of CMOS elements. Further the design is implemented using 180nm technology in CADENCE tool and is simulated for number of test cases. The proposed design found to be effective in comparison with the previously designed circuits. The simulation results show the effectiveness in terms of area, speed and power dissipation for a single stand by cell.

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